// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vdh_arbit_reg_offset.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:43 Create file
// ******************************************************************************

#ifndef __VDH_ARBIT_REG_OFFSET_H__
#define __VDH_ARBIT_REG_OFFSET_H__

/* VDH_ARBIT Base address of Module's Register */
#define SOC_VDH_ARBIT_BASE                       (0x2000)

/******************************************************************************/
/*                      SOC VDH_ARBIT Registers' Definitions                            */
/******************************************************************************/

#define SOC_VDH_ARBIT_VDH_ARBIT_STATE0_REG     (SOC_VDH_ARBIT_BASE + 0x0)  
#define SOC_VDH_ARBIT_U0_SOFTRST_STATE0_REG    (SOC_VDH_ARBIT_BASE + 0x10) 
#define SOC_VDH_ARBIT_U0_SOFTRST_STATE1_REG    (SOC_VDH_ARBIT_BASE + 0x14) 
#define SOC_VDH_ARBIT_U1_SOFTRST_STATE0_REG    (SOC_VDH_ARBIT_BASE + 0x10) 
#define SOC_VDH_ARBIT_U1_SOFTRST_STATE1_REG    (SOC_VDH_ARBIT_BASE + 0x1C) 
#define SOC_VDH_ARBIT_U0_R_2TO1_ARBIT_REG      (SOC_VDH_ARBIT_BASE + 0x20) 
#define SOC_VDH_ARBIT_U0_W_2TO1_ARBIT_REG      (SOC_VDH_ARBIT_BASE + 0x24) 
#define SOC_VDH_ARBIT_U0_RCMD_C2A_FIFO_REG     (SOC_VDH_ARBIT_BASE + 0x30) 
#define SOC_VDH_ARBIT_U1_RCMD_C2A_FIFO_REG     (SOC_VDH_ARBIT_BASE + 0x34) 
#define SOC_VDH_ARBIT_U0_WCMD_C2A_FIFO_DG_REG  (SOC_VDH_ARBIT_BASE + 0x38) 
#define SOC_VDH_ARBIT_U1_WCMD_128B_FIFO_DG_REG (SOC_VDH_ARBIT_BASE + 0x3C) 
#define SOC_VDH_ARBIT_VDH_ARBIT_AWVALID_REG    (SOC_VDH_ARBIT_BASE + 0x40) 
#define SOC_VDH_ARBIT_VDH_ARBIT_AWREASY_REG    (SOC_VDH_ARBIT_BASE + 0x44) 
#define SOC_VDH_ARBIT_VDH_ARBIT_WVALID_REG     (SOC_VDH_ARBIT_BASE + 0x48) 
#define SOC_VDH_ARBIT_VDH_ARBIT_WREADY_REG     (SOC_VDH_ARBIT_BASE + 0x4C) 
#define SOC_VDH_ARBIT_VDH_ARBIT_ARVALID_REG    (SOC_VDH_ARBIT_BASE + 0x50) 
#define SOC_VDH_ARBIT_VDH_ARBIT_ARREADY_REG    (SOC_VDH_ARBIT_BASE + 0x54) 
#define SOC_VDH_ARBIT_VDH_ARBIT_RVALID_REG     (SOC_VDH_ARBIT_BASE + 0x58) 

#endif // __VDH_ARBIT_REG_OFFSET_H__
